Intern - HBM SoC Physical Design Engineer

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Physical Design team is responsible for implementing advanced High Bandwidth Memory (HBM) SoC and base die designs that enable next-generation AI, high-performance computing, and data center solutions. The team collaborates across architecture, RTL, verification, DFT, and signoff engineering to deliver high-performance, power-efficient silicon while developing innovative design methodologies and automation solutions. As an SoC Physical Design Intern on the HBM team, you will work alongside experienced engineers to support the implementation of advanced HBM SoC designs. You will gain hands-on experience with physical design methodologies, timing analysis, signoff flows, and automation while contributing to the development of next-generation memory products that power AI and high-performance computing applications. Responsibilities Support the physical implementation of SoC design blocks, including floorplanning, placement, clock tree synthesis, routing, and physical optimization activities. Analyze timing, power, area, congestion, and physical verification results to find opportunities for design improvement and optimization. Assist with static timing analysis, timing closure, and debugging across multiple operating modes and process corners. Develop and enhance automation tools, scripts, reports, and workflows using Python, Tcl, shell scripting, and AI-assisted solutions. Collaborate with multi-functional engineering teams to document results, participate in design reviews, and present technical findings. Minimum Qualifications 0-2 years of relevant experience through internships, research, coursework, or academic projects in ASIC design, VLSI, digital IC design, computer architecture, or physical design. Currently pursuing a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field. Knowledge of ASIC design flow concepts, including synthesis, place-and-route, static timing analysis, and physical verification. Understanding of timing fundamentals such as setup/hold analysis, clock skew, timing constraints, and critical path analysis. Experience with programming or scripting languages such as Python, Tcl, Perl, and/or Shell. Strong analytical, problem-solving, communication, and teamwork skills. Familiarity with AI-enabled tools and large language models (LLMs) such as Copilot, Claude, or similar technologies. Preferred Qualifications Experience through coursework, research, or internships with RTL-to-GDSII implementation flows. Familiarity with industry-standard EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent platforms. Knowledge of multi-mode, multi-corner timing analysis, power intent methodologies, power delivery networks, or IR/EM analysis. Understanding of DRC, LVS, parasitic extraction, signal integrity, clock tree synthesis, or congestion analysis concepts. Experience developing automation solutions, dashboards, or engineering workflows using Python, Tcl, or related scripting languages. Interest in HBM, DRAM, advanced packaging, memory-centric SoCs, or high-performance digital design. The US base salary range that Micron Technology estimates it could pay for this full-time position is: $38.84 - $50.24 an hour Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure