SENIOR ENGINEER HBM LAYOUT

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Introduction The High Bandwidth Memory (HBM) Layout Development team at Micron invents innovative memory solutions enabling next-generation Artificial Intelligence (AI), High Performance Computing (HPC), and data-centric applications. Our engineers work alongside global design, verification, and product development teams to deliver industry-leading semiconductor technologies that power the future of computing. Position Overview As a Layout Engineer within Micron's HBM organization, you will help build the physical implementation of advanced analog, mixed-signal, and custom digital circuits for groundbreaking memory products. You will work with diverse teams across Micron's global engineering network to create high-quality layout solutions that meet performance, quality, and schedule goals. This role provides a chance to engage with complex semiconductor technologies that support powerful innovations in AI and next-generation computing systems. Responsibilities Build and develop high-quality analog, mixed-signal, custom digital, and full-chip layout solutions for advanced HBM products. Perform and drive physical verification activities, including DRC, LVS, antenna checks, quality reviews, and documentation to ensure build integrity. Lead layout planning, area estimation, scheduling, and execution activities across multiple projects while meeting quality and delivery commitments. Collaborate with global build, circuit, verification, and product engineering teams to resolve layout challenges and optimize design performance. Leverage AI-enabled tools and data-driven methodologies to improve engineering efficiency, layout quality, and development productivity. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI Engineering, or a related technical field. 5+ years of experience in analog/custom layout development using advanced CMOS technologies, including planar and FinFET process nodes. Skilled in Cadence Virtuoso Layout Suite (VLE/VXL) and Mentor Graphics Calibre for DRC, LVS, and physical verification tasks. Hands-on experience crafting complex analog and mixed-signal circuit layouts such as PLLs, ADCs, DACs, LDOs, bandgaps, charge pumps, comparators, temperature sensors, and related blocks. Strong understanding of analog layout fundamentals, including matching, electromigration, latch-up prevention, parasitic effects, IR drop, signal integrity, coupling, and reliability considerations. Preferred Qualifications Proven experience supporting multiple successful tape-outs in advanced semiconductor technologies. Demonstrated ability to manage multiple layout projects while maintaining high-quality standards and meeting aggressive schedules. Strong problem-solving skills in custom layout verification, debugging, and physical build optimization. Experience collaborating with geographically distributed engineering teams in a complex product development environment. Familiarity with AI-assisted engineering workflows, automation tools, or data-driven approaches that improve design efficiency and decision-making. "The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position." We are an industry leader in innovative memory and storage solutions transforming